1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
Priority is claimed on Japanese Patent Application No. 2007-337091, filed Dec. 27, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, techniques related to semiconductor devices and methods of manufacturing the same have rapidly been progressing, and various techniques have been developed.
For example, Japanese Laid-open Patent, Publication No. H09-260536 discloses a new structure of a semiconductor device. In the structure, a flexible wiring substrate is provided on the bottom surface of a semiconductor chip through an elastomer. Electrode pads provided on the semiconductor chip are electrically connected to lead portions of wirings provided at an opening provided on the wiring substrate. External terminals are provided on the bottom surface of the wiring substrate. A seal made of an insulating resin covers the electrode pads and the lead portions that are in the opening.
However, the electrode pads are connected to the lead portions at the opening provided on the wiring substrate, causing a problem in that the lands are positioned far from the electrode pads. Since the operation speed is becoming faster and faster year after year, reduction in the operation speed might occur if the lands are positioned far from the electrode pads.
Since the opening is provided around the electrode pads, external terminals cannot be arranged therein, and therefore the number of external terminals that can be arranged on the connection region of the wiring substrate and the semiconductor chip is small in some cases.
In this case, external terminals have to be arranged outside the connection region, requiring a larger wiring substrate, and therefore a larger package of a semiconductor device, which is against the recent trend toward thinner and lighter semiconductor devices. Recently, the increasing number of external terminals has been required for semiconductor devices. Therefore, ways to increase the number of external terminals to be arranged on the connection region of the wiring substrate and the semiconductor device have been attracting more and more attention.
Since the semiconductor chip is mounted on the wiring substrate, the wiring substrate has to be larger in size than the semiconductor chip even if all of external terminals can be included inside the area where the semiconductor chip is mounted, requiring a larger package of the semiconductor device, which is also against the recent trend toward thinner and lighter semiconductor devices.
Further, the opening has to be provided on the wiring substrate, and therefore there is a waste region to be cut down, making the wiring substrate larger. If a larger wiring substrate is used, the number of wiring substrates that can be obtained from one original substrate decreases, causing higher costs of forming wiring substrates.
Moreover, the semiconductor chip is mounted on the wiring substrate through the elastomer (elastic member) in the structure so that stress caused by a difference in thermal expansion coefficients between the semiconductor chip and the wiring substrate is reduced, and thereby the reliability of a secondary mounting is enhanced. However, costs of manufacturing the semiconductor device become higher since the elastomer is expensive, and the semiconductor device becomes thicker due to the elastomer, which is also against the recent trend toward thinner and lighter semiconductor devices.
Japanese Laid-open Patent, Publication No. 2002-110856 discloses a method of mounting interposers formed by cutting a wiring substrate into pieces for each element on non-defective semiconductor chips provided on a semiconductor wafer and then cutting the semiconductor wafer into semiconductor chips.
In this method, however, the interposers respectively having substantially the same sizes as those of the semiconductor chips are mounted on the semiconductor chips provided on the semiconductor wafer along dicing lines with no space thereamong. Therefore, the interposers mounted on adjacent semiconductor chips contact each other, and the mounting positions of the interposers might be displaced when electrode pads are aligned on a circumference of each semiconductor chip.
If displacement of the interposers occurs, the cutting precision when the semiconductor wafer is cut into semiconductor chips deteriorates, causing deterioration in the dimensional precision of the semiconductor device.
Further, there is no room for an adhesive to spread, and thereby the adhesive might leak into an adjacent semiconductor chip when the interposers respectively having substantially the same sizes as those of the semiconductor chips are mounted on the semiconductor chips using the adhesive. When the adhesive leaks into the adjacent semiconductor chip, an adjacent interposer cannot precisely be mounted on the adjacent semiconductor chip, and might cover electrode pads on the adjacent semiconductor chip.
Since the interposers respectively having substantially the same sizes as those of the semiconductor chips are mounted on the semiconductor chips, stress caused by a difference in thermal expansion coefficients between the interposers and the semiconductor chips cannot be reduced, decreasing the reliability of a secondary mounting of the semiconductor device. Further, voids might occur between the semiconductor chips and the interposers, causing cracking to occur when the semiconductor device is reflowed. Moreover, the size of each interposer has to be changed according to the size of each semiconductor chip since each interposer is formed for each element.
As another example of semiconductor manufacturing methods, Japanese Laid-open Patent, Publication No. 2006-216823 discloses a method of forming wiring substrates to match semiconductor chips provided on a semiconductor wafer, mounting the wiring substrate on the semiconductor wafer, and collectively cutting the semiconductor wafer and the wiring substrate.
However, grooves are provided on the wiring substrate of the semiconductor device. Therefore, lands are positioned far from electrode pads, causing operation delay as explained above. Further, external terminals need to be aligned on the semiconductor substrate outside the regions where the semiconductor chips are arranged, necessitating a larger package size of the semiconductor device. Moreover, waste regions to be cut down increase. Thereby, the number of wiring substrates that can be obtained from one original substrate decreases, causing higher costs of forming wiring substrates.
When the wiring substrate is collectively mounted on the semiconductor wafer, little displacement on one side of the wiring substrate causes large displacement on the other side thereof, necessitating a precise position setting of the wiring substrate.
Further, a layout of the wiring substrate is determined for each semiconductor wafer, the size and the layout of the wiring substrate need to be changed when the size and the layout of the semiconductor chip is changed.